Products & Solutions

ARC® VRaptor™ Multicore Architecture

A Configurable, Scalable Solution for Complex Media Processing Tasks

The ARC® VRaptor Multicore Architecture is a new configurable solution that scales to meet the high definition media processing requirements in a wide array of consumer devices. It will support multiple ARC configurable CPUs with media extensions, multiple vectorized 128-bit SIMD processors, high performance streaming I/O, and domain specific accelerators. All will be connected by ARC's new active communication channels technology. The ARC VRaptor Multicore Architecture is the foundation of ARC’s next-generation Multimedia Subsystems, including the recently introduced 402V, 406V, 407V, and 417V Subsystems.

Legacy "fixed architectures" aren't well suited to meet the requirements of highly complex – yet power sensitive – media-oriented processing tasks. For example, a generic 32-bit RISC processor could require as much as 18 GHz for standard definition (SD) H.264 encode or 5 GHz for MPEG-4 encode. ARC's VRaptor Multicore Architecture leverages the power of its patented configurable technology to deliver an elegant implementation that capitalizes upon application-level parallelism. ARC's VRaptor Multicore Architecture will require only 200 MHz for SD H.264 encoding, while retaining all of the benefits of a programmable solution.

Vectorized SIMD Processors

Multiple configurations of ARC’s award-winning 128-bit SIMD processors are capable of handling a variety of media operations such as deblock filters, pixel transforms, and audio processing in the ARC VRaptor Multicore Architecture. Each have a rich array of arithmetic, logical, and control instructions, configurable and programmable vector and scalar registers, as well as a set of application specific instructions that are specifically tailored to accelerate complex operations. They are connected via ARC’s active communication channels technology to optional configurable media accelerators that are capable of performing repetitive, computationally intensive tasks such as motion estimation or entropy encoding in the case of video encoding, and to VRaptor's I/O devices for DMA operations.

Programmable

Because VRaptor is a heterogeneous multicore architecture, the configurable ARC CPUs, vectorized SIMD media processors, dedicated hardware accelerators, and I/O devices are programmed with the same tools and interconnected with ARC’s active communication channels technology. This simplifies the software development process and enables SoC designers to easily include codecs and algorithms over time, extending the market life of chips based upon the VRaptor Architecture.

Scalable

The VRaptor Architecture can scale from a single configurable ARC 710D CPU up to multiple configurable ARC 750D CPUs, each with multiple media processors, multiple accelerators, and multiple I/O devices. The smallest instantiation is less than 0.5 mm2 in a 90nm process.

Tools

Each vectorized media processor was created using ARC’s patented configurable technology, and extended from a base configuration of an ARC 750D CPU. This ensures instruction-level compatibility with the ARCompact™ ISA and allows support by the same toolsets that support other ARC subsystems and processors. Included are MetaWare and GNU tools, which provide extensive profiling, debug, and assembly level support. These are being enhanced to include a vectorized compiler and fast models.

Low Power

As with all ARC products, the VRaptor Architecture has been designed with low power requirements in mind, including power down features, and real time software and hardware tradeoffs.

Active Communication Channels Technology

The patent-pending active communication channels technology in the VRaptor Multicore Architecture is an active channel protocol that is based around Remote Invocation. It provides point-to-point links in hardware between the VRaptor cores, VRaptor accelerators and VRaptor I/O elements, and carries commands as well as data. The active communication channels technology is supported directly by new instruction extensions in ARC’s configurable ISA, and eliminates message interpretation overhead. It also provides for a unified programming model that simplifies the programming overhead that is often associated with multi-processor architectures.