Software & Tools
VTOC® for SoC Models
100% Cycle Accurate Modeling of ARC and Non-ARC IP
ARC® VTOC® products use the technology behind the ARC xCAM Cycle Accurate Model generator to automatically provide 100% cycle accurate C++ and SystemC models of customers’ ARC and/or non-ARC IP written in Verilog. Since the models are pure software and can be compiled to binary, they also are ideal for secure shipment of IP models to third parties.
VTOC models enable:
- Reuse of legacy RTL IP in C++/SystemC architectural exploration of new designs. This is ideal for next generation Electronic System Level (ESL) design flows and tools
- Creation of virtual platforms for early development and system verification of complex SoCs with their associated software before real silicon is available
Benefits
Reduce Time to Market
- Save tens of man-months of SystemC model development work
- Automatically generate 100% cycle accurate models from any synthesizable Verilog RTL
- Parallelize hardware and software development
Minimize Risk
- 100% cycle accurate models - no errors like with hand-generated models
- Reuse legacy RTL IP in C++/SystemC architectural exploration of new designs
- Find problems earlier through early software development, early verification of SoC with software, and fast hardware iterations
Increase Developer Productivity
- Distribute models anywhere - allows engineers in different locations to easily work on same versions of hardware models and software
- SystemC models can connect to wider co-development tool flows to help productivity
- VTOC-generated SystemC models plug-and-play with CoWare Platform Architect, Novas Verdi, Cadence SimVision and other system design tools
top
VTOC® Flow Diagram
top
The VTOC® Suite
ARC® VTOC® is a comprehensive suite of software products that support the move to electronic system level (ESL) design environments.
- VTOC Generate
Takes designs in Verilog and synthesizes a 2-value cycle accurate C++ or SystemC model that can be targeted automatically for use in C++, SystemC, or HDL environments under Microsoft Windows or Linux.
- VTOC Validate
Functionally verifies the C++ model created by VTOC Generate against the behaviour of the original RTL to enable early identification of potential problems in initialization, and use of 4-value simulation vs. 2-value synthesized model behaviour.
- VTOC RunTime
Provides comprehensive command line interfaces and APIs to access and debug the running model.
- VTOC IP eXchange
Provides controlled distribution of the secure C++ models created by VTOC Generate for use as evaluation platforms. Each export model has the performance of a VTOC model, with the security of binary compiled code and the ability to execute in C++, SystemC, and HDL environments under Microsoft Windows and Linux.
top
|
