Software & ToolsCo-Design & SimulationCo-Design with Unique Modeling and Simulation ProductsHow much of your software development team's time is spent waiting for FPGA boards or for access to RTL simulators? Advances in co-design and simulation have created more opportunities for first-pass success because now developers can simulate the entire system on a host PC prior to tape-out. ARC offers a variety of simulation products encompassing the entire scope from automatically generated cycle accurate simulators to fast, functional instruction set simulators. To enable SW development in an full SoC context ARC provides a methodology package that allows virtualisation of the SW visible SoC components, such as peripheral registers, memories and interrupts. For further information contact your local ARC representative. BenefitsReduce Time to Market and Minimize Risk
Differentiate to Keep Competitive Edge
Co-Design and Simulation Tools Selector ChartChoose the Right Tool for the JobAlthough simulation is a proven tool for decreasing time-to-market, it is important to match one’s needs with the strengths of the various simulation technologies available. ARC offers a broad suite of simulation products that enable hardware / software co-design prior to silicon being available. Each product differs in its intended use model, speed, accuracy, and debug views.
Metaware ISS for Quick SW Routine DevelopmentMetware ISS is provided by default within the Metaware SW development toolkit. It enables easy development, test and debug of small SW components. The ISS provides additional capabilities that are not available on hardware, such as:
Within the Metaware ISS a cycle estimation component (CES) can be activated. It allows estimation of machine cycles when executing programs. The CES also includes a cache thrash analysis routine to point out cache thrashing. Simulation performance of the Metaware ISS goes up to ~2 MIPS. xISS Turbo Fast ISS for Full Application DevelopmentxISS enables fast development, software test and debug. ARC xISS and ARC xISS Turbo are high-performance instruction-set level simulations that increase software development productivity at every stage of ARC-Based product development. ARC xISS Turbo uses advanced Just-in-Time Compiler technology to produce 200+ MIPS (millions of instructions per second) performance, while ARC xISS provides affordable yet advanced ISS capability at ~20 MIPS performance. xCAM Generate for Instant Cycle Accurate Model CreationWith the addition of ARC xCAM, the ARChitect IP Configurator can automatically generate cycle accurate models of any customized ARC IP, allowing code to be tuned on the exact hardware configuration being considered. Executing at between 40kHz to 60kHz, xCAM models are available within minutes of a configuration being finalized, enabling a genuinely iterative design approach. xCAM models provide detailed cycle and “programmer’s view” information for profiling and they easily import into SystemC co-development tools. |
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