Tools & Software
Cycle-Accurate and Instruction Set Simulators (CAS & ISS)
ARC™'s cycle accurate simulators (CAS) provide a fast simulation platform to run code and analyze the performance of a system with a high degree of cycle accuracy. The CAS fully supports ARC processors' configurable and extendible architecture. It can be configured from the MetaWareŽ Debugger to match the specific configuration of users' processor hardware. In addition users can extend the CAS with extension instructions, core registers, auxiliary registers, and condition codes to create a completely customized model of their own processor.
The Instruction Set Simulator (ISS) is the default target loaded by the MetaWare Debugger for a software debug session. The ISS is often the only target available for many firmware engineers because they typically develop applications before the hardware exists. Usually the hardware description language (HDL) has not yet been finalized or the FPGA configurations synthesized.
Even when firmware is developed after the SoC has been finalized, there may be insufficient FPGA boards for firmware engineers. HDL simulation seats are both expensive and too slow for extensive firmware debug sessions. The ISS runs at 1-2MIPS and about 2000x the speed of most HDL simulations. Full-size and complex builds can be run to show not only code correctness but that the code size and mapping is correct. The ISS is also extendible to match the profile of the configurable and extendible ARC core.
Both types of simulators can be integrated with the MetaWareŽ profiler. Developers can gather an immense amount of information to aid in optimizing their embedded software, including:
- Cycle count
- Killed cycles due to branches
- Stall cycles
- Instruction and statement hit counts
- Function entry counts
ARC's simulators for ARC processors deliver ease of use and high performance enabling developers to create optimized solutions faster.
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