Tools & Software

Modelling

ARC's simulation and modeling capabilities enable customers to take the maximum advantage of ARC's configurable IP. Cycle-accurate models allow SoC designers to compare alternative configurations and to verify that key algorithms and code sections meet target performance goals. Instruction set simulators provide faster platforms for ARC-Based™ software development in parallel with hardware creation.

ARC® xCAM products quickly and automatically generate 100% cycle-accurate models of configured ARC IP, allowing for co-development of software and hardware early in the design cycle.

ARC® VTOC® products generate 100% cycle-accurate C++ and SystemC models of ARC and/or non-ARC IP. The resulting models enable complete architectural exploration, early development of software, and system verification of SoCs incorporating IP from numerous vendors and accompanying software.

ARC® xISS Turbo provides 200+ MIPS high-speed ISS performance using Just-in-Time (JIT) compile technology. ARC's standard xISS tool provides 20 MIPS performance without using JIT. The MetaWare Debugger includes a 2 MIPS built-in ARC ISS that also can be used in environments where higher speed simulation performance of the xISS products is not critical to developer productivity.

ARC® MetaSim provides a simple way to allow ARC simulations to run via the MetaWare debugger to link and control RTL simulations of outside SoC IP contents to greatly speed the co-simulation of the entire SoC system.

Hardware assisted RTL simulation, and JTAG emulation, is available through our third-party partners.