Products & Solutions

ARC® Energy PRO Technology

System-Level Solutions for SoC Power Management

ARC® Energy PRO™ technology combines hardware IP, software and integration with industry-standard EDA flows, to offer a system-level solution for the design of ultra-low-power SoCs.

Working at every level – from software application and operating system to final chip layout – Energy PRO technology addresses one of the most taxing problems for today's SoC designers: conserving energy while increasing functionality. It takes the battle beyond established fine-grained clock-gating and multi-Vt implementations, enabling advanced techniques such as dynamic voltage and frequency scaling (DVFS) and domain-level clock gating.

The impact of these developments is far-reaching. Not only does Energy PRO enable an SoC design that is truly optimized for both dynamic and static power, it also provides a mechanism for controlling power consumption at run-time. So the device can dynamically tune its behavior to the changing demands placed upon it. As a result, Energy PRO can cut SoC power consumption by a factor of four or more depending on the application.

Advanced Hardware

At the heart of every Energy PRO-equipped device is a dedicated power management unit (PMU). The PMU directly and intelligently controls clock gating, voltage domains and DVFS functions, as well as ensuring correct sequencing of power management actions. It also guarantees that hardware blocks transition gracefully between power-saving modes.

Energy PRO includes four key hardware-based power management techniques.

• Functional clock gating can be used to shut down the clock to a functional block (under PMU control) when it reports that it is idle.
• Architectural clock gating ensures that clocks are switched off at the highest possible level, engaging processor sleep modes when there are no tasks to run.
• Power shut-off takes the core into an even “deeper” sleep mode to save leakage power.
• DVFS tailors voltage and clock frequency to the requirements of the currently running application.

And the power of Energy PRO is not restricted to the ARC core itself. An interface to the wider SoC allows the PMU to apply the same intelligent dynamic control strategies to other IP blocks within the device, including logic, memory and peripheral devices.

Energy PRO also takes advantage of industry-standard low power standard cell libraries to implement key hardware blocks – such as isolation cells and level shifters – that assist in implementing a cohesive low-power design strategy.

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Software Puts You in Control

Just as important as the hardware is the software which gives designers and programmers control over Energy PRO functions. These include enhancements to the core ARC instruction set architecture (ISA), providing direct control of the PMU and other blocks; and the ability to add custom instructions for power management purposes.

At a higher level, Energy PRO also includes a software API that can be incorporated into an operating system or used directly by an application to control the hardware power management features. Programming support is integrated via ARC's MetaWare® development tools.

Software developers are further empowered by enhancements to ARC's MQX RTOS that take advantage of Energy PRO. The MQX-EP RTOS provides applications with an interface to power management features and can itself record power management activity. This information can then be used to fine tune the power profile of the device.

Such enhancements provide tight control of power budgets. For instance, core voltage and clock rate can be scaled according to the requirements of individual threads; or the OS may be authorized to shut down the core when no threads are running.

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EDA Integrated

Implementing a system-level SoC power management strategy requires integration with industry-standard EDA flows. Like all of ARC's key technologies, Energy PRO is supported by first-class design and verification tools, allowing its integration into any industry-standard RTL-to-GDSII flow.

Based on the ARChitect™ Processor Configurator, captures the low-power design intent at the time the ARC core is configured, and conveys that intent through the flow to tape-out, using industry standards such as UPF or CPF, or the designer's own preferred data interchange format.

In addition, we have worked with Cadence Design Systems and Virage Logic to produce a complete, validated reference design methodology (RDM) that offers designers a simple, highly integrated and automated development process. The RDM provides accurate simulation of power-down modes, automated insertion of isolation cells and level shifters during synthesis, and placeand-route tools that can accommodate the use of "voltage islands".

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