Products & Solutions
ARC® EP30 Core
Fully-Featured 32-Bit Embedded CPU/DSP Core Reduces Power 75% or More
The ARC® EP30 configurable processor is an ultra-low-power CPU/DSP core, intended as a complete processor solution for applications such as portable and mobile appliances, wireless connection management and RTOS-based systems. The EP30 is a code-compatible evolution of the successful ARC 600 Series processors, and uses ARC's unique Energy PRO system-level power management technology to reduce power consumption by 75% or more in typical applications.
The ARC EP30 includes powerful DSP options and, like all ARC cores can be extended with custom instructions for more efficient SoC implementations. Its flexible, configurable memory architecture, including single-cycle closely-coupled memories (CCMs) and data and instruction caches, makes it ideal for RTOS-based applications.
Content On This Page
| Benefits | Characteristics | Block Diagram | Highlights |
| EP30 Power Modes | Features |
Benefits
Differentiate With Lowest Possible Power and Configurability
- Extend battery life 75% or more through power saving modes of operation
- Choose only the features required; even de-configure the EP 30 to create the world's smallest, lowest-power licensable core
- Create unique custom features through configurability and custom extensions
Differentiate With Performance
- Accelerate signal processing algorithms with built-in DSP features
- Optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores
- Achieve 100-times performance improvements for critical routines with user-defined instruction and register extensions
Reduce Time to Market and Minimize Risk
- 140+ customers with 300+ million commercially proven customer chips shipping annually
- Complete development tools and design flow support, including industry-leading co-design
- Silicon-proven, pre-verified options cut design cycle time
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ARC EP30 Characteristics
| Product Characteristics in 90nm Process* |
| Max Clock Frequency |
520 MHz |
| Power Consumption |
0.05 mW/MHz |
| Silicon Area |
0.26 mm˛ |
|
Frequency (worst case condition) is based on TSMC GT. Power (typical condition) and area are
based on TSMC LP process. Data is for base configuration, placed and routed design.
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ARC EP30 Block Diagram
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Highlights
- Complete processor solution combines best-in-class performance, die size and system resource requirements.
- Flexible memory design, including caches and closely coupled (single-cycle) memories, suits RTOS-based applications.
- ARC's configurable architecture allows SoC designers to include only the processor features they require, resulting in more efficient implementations.
- Energy PRO power management features give the designer control over advanced energy-saving techniques – not just in the core, but across the SoC.
- Multiple power modes produce up to 75% active power savings: and reduce idle power to 50µW.
- User-defined instruction and register extensions deliver up to 100-times performance improvements for critical routines.
- Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms.
- Optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores.
- ARCompact™ 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets.
- JTAG debug port and optional embedded hardware breakpoints facilitate software debug.
- Delivered as synthesizable RTL source code (Verilog® ), the ARC EP30 core is fully compatible with industry standard design methodologies and tool flows.
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ARC® EP30 Power Modes
Example EP30 Configuration:
200 MHz Design in TSMC 90G Process |
| Dynamic Power (mW) |
Leakage Power(mW) |
| Cell | RAM | Total | Cell | RAM | Total |
| 11.5 |
21.5 |
33.0 |
0.4 |
1.1 |
1.5 |
| Power Saving Mode |
Power
(mW) |
% of Baseline |
| Baseline Measurement @200MHz, 1.0V |
34.4 |
100% |
| Reduced clock frequency @50MHz, 1.0V |
9.8 |
28% |
| Reduced clock and voltage @50MHz, 0.7V |
6.8 |
20% |
| Sleep mode, clocks only @200MHz, 1.0V |
7.1 |
21% |
| Sleep mode, clock gated off at source @1.0V |
1.5 |
4% |
| Complete core power down, except “always on” logic |
0.2 |
1% |
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ARC® EP30 Configurable Core Features
CPU Architecture - Five-stage instruction pipeline
- Static branch prediction
- 32-bit data, instruction and address buses
- Scoreboarded data memory pipeline to reduce data stalls
- Configurable instruction cache, 2KByte to 32KByte
- Configurable data cache, 2KByte to 32KByte
- Single-cycle instruction CCM (Closely Coupled Memory), 1KByte to 512KByte
- Single-cycle data CCM, 2KByte to 256KByte
- Configurable endianness
- Up to 32 two-level interrupts
Energy PRO Power Management - Dedicated power management unit (PMU) controls power management modes, sequencing and run-time behavior
- Function-level clock gating
- Architectural-level clock gating
- Power domains and power shut-off
- Dynamic voltage and frequency scaling
- Enables true multi-Vt design
- External interface for SoC-wide power management
- Multiple low-power modes
- API- and OS-level software control
- High-efficiency pipeline
ARCompact™ ISA
- 16- and 32-bit instructions for high code density
- No overhead for switching between 16- and 32-bit
- Single-cycle instruction execution
- ISA extended to provide system-wide power management functions
- Up to 128 dual or single operand instruction codes available for user-defined extensions
- Up to 64 directly addressable core registers and 32 conditional execution codes
- Flexible addressing modes
Registers - 16 or 32 entry register file in base processor, extendible to 60
- 26 general purpose registers, extendible to 54
- 32-bit auxiliary register space for single-cycle, unarbitrated data storage and retrieval
FPX Floating Point Extensions View more information on ARC FPX DSP Extensions - 16- and 32-bit MUL and MAC instructions
- Parallel execution of MUL, MAC and other ALU operations
- Saturating arithmetic instructions
- Zero overhead loop support
ARC XY Advanced DSP Subsystem - Full DSP performance using configurable banks of XY memory
- Eliminate DSP and logic blocks
- Consolidate development environment
- Includes ARC DSPlib with extensions such as: Dual FFT, Viterbi, CRC, 24x24MAC
View more information on the ARC XY Subsystem Host Interface/Debug Features - Software and hardware breakpoints with cascadable triggers
- JTAG interface to host tools
- Debug host can access all registers and CPU memory
- Supported by leading debuggers including Green Hills Software and MetaWare®
- SmaRT real-time trace facility
System Interface - Configurable port complies with industry standard AMBA/AHB or BVCI
- Slave interfaces exposed for loading optional instruction and data CCMsRight-hand sidebar
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ARC International pioneered configurable processor technology and is the leader with over 140 customers worldwide who collectively ship more than 300 million ARC-Based™ chips annually.
Applications
Consumer Products
- Personal audio and image players
- Cellular handsets
- Digital radios
- Toys
Mobile Communication Products
Medical Products
- Implantable monitors
- Pacemakers
- Hearing aids
General Purpose
- Low-power microcontrollers
ARC® Energy PRO™ technology combines hardware IP, software and an advanced EDA flow, to offer a system-level solution for the design of ultra-low-power SoCs.
Energy PRO technology works at every level – from software application and operating system to final chip layout. It takes the energy-saving battle beyond established fine-grained clock-gating and multi-Vt implementations, enabling advanced techniques such as dynamic voltage and frequency scaling (DVFS) and domain-level clock gating.
These developments allow optimization of power performance during design; and just as importantly provide a mechanism for controlling power consumption at run-time. So your device can dynamically tune its behavior to the changing demands placed upon it.
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