Products & Solutions
ARC® EP20 Core
Ultra-Low-Power Cacheless 32-Bit Embedded CPU/DSP Core
The ARC® EP20 processor is an ultra-low-power cacheless CPU/DSP core, designed for embedded microcontroller applications ranging from hard real-time systems, to storage and medical devices. The EP20 uses ARC's unique Energy PRO system-level power management technology to reduce power consumption by a factor by 75% or more. Equipped with powerful and flexible DSP options, the EP20 CPU is ideal for SoC applications that include both conventional computation and signal processing algorithms. Using ARC's unique configurable technology, the EP20 can be “de-configured” to create the world's smallest, lowest-power licensable core.
Content On This Page
| Benefits | Characteristics | Block Diagram | Highlights |
| Application Examples | Features |
Benefits
Differentiate With Lowest Possible Power and Configurability
- Extend battery life 75% or more through power saving modes of operation
- Choose only the features required; even de-configure the EP 20 to create the world's smallest, lowest-power licensable core
- Create unique custom features through configurability and custom extensions
Differentiate With Performance
- Accelerate signal processing algorithms with built-in DSP features
- Optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores
- Achieve 100-times performance improvements for critical routines with user-defined instruction and register extensions
Reduce Time to Market and Minimize Risk
- 140+ customers with 300+ million commercially proven customer chips shipping annually
- Complete development tools and design flow support, including industry-leading co-design
- Silicon-proven, pre-verified options cut design cycle time
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ARC EP20 Characteristics
| Product Characteristics in 90nm Process* |
| Max Clock Frequency | 500 MHz |
| Power Consumption |
0.03 mW/MHz |
| Silicon Area |
0.17 mm˛ |
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Frequency (worst case condition) is based on TSMC GT. Power (typical condition) and area are based on TSMC LP process. Data is for base configuration, placed and routed design.
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ARC EP20 Block Diagram
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Highlights
- A cacheless design and closely coupled (single-cycle) memories (CCMs) provide the fast computation and deterministic response required in hard real-time applications.
- ARC's configurable architecture allows SoC designers to include only the processor features they require, making the EP20 the world's smallest, lowest-power licensable core.
- Energy PRO power management features give the designer control over advanced energy-saving techniques – not just in the core, but across the SoC.
- User-defined instruction and register extensions deliver up to 100-times performance improvements for critical routines.
- Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms.
- Optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores.
- ARCompact™ 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets.
- JTAG debug port and optional embedded hardware breakpoints facilitate software debug.
- Delivered as synthesizable RTL source code (Verilog® ), the ARC EP20 core is fully compatible with industry standard design methodologies and tool flows.
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Application Examples
|
90nm G Process |
90nm G Process |
90nm G Process |
|---|
Freq
(MHz) |
Area
(mm2) |
Power
(mW/MHz) |
High performing real time controller
8K + 8K CCMs, 32 register file
BVCI bus
Extended arith. instructions
DSP instructions and XMAC
Speed-optimized synthesis | Without CCMs | 281 | 0.25 | 0. | | With CCMs | 281 | 0.67 | | Basic 32-bit controller
8K + 8K CCMs, 16 register file
BVCI bus
Basic instruction set
Area-optimized synthesis | Without CCMs | 155 | 0.12 | 0.02 | With CCMs | 155 | 0.55 | 0.11 | Based on placed and routed design in TSMC process using Virage libraries and RAMs.
Clock frequency is based on worst case conditions
Power numbers are based on typical conditions and assume rated voltage with all functional blocks powered on and clocked.
Using alternate cell and memory libraries or design flow may yield lower or higher figures. |
|---|
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ARC® EP20 Configurable Core Features
CPU Architecture- Five-stage instruction pipeline
- Static branch prediction
- 32-bit data, instruction and address buses
- Scoreboarded data memory pipeline to reduce data stalls
- Single-cycle instruction CCM (Closely Coupled Memory), 1KByte to 512KByte
- Single-cycle data CCM, 2KByte to 256KByte
- Configurable endianness
- Up to 32 two-level interrupts
Energy PRO Power Management- Dedicated power management unit (PMU) controls power management modes, sequencing and run-time behavior
- Function-level clock gating
- Architectural-level clock gating
- Power domains and power shut-off
- Dynamic voltage and frequency scaling
- Enables true multi-Vt design
- External interface for SoC-wide power management
- API- and OS-level software control
- High-efficiency pipeline
ARCompact™ ISA- 16- and 32-bit instructions for high code density
- No overhead for switching between 16- and 32-bit
- Single-cycle instruction execution
- ISA extended to provide system-wide power management functions
- Up to 128 dual or single operand instruction codes available for user-defined extensions
- Up to 64 directly addressable core registers and 32 conditional execution codes
- Flexible addressing modes
Registers- 16 or 32 entry register file in base processor, extendible to 60
- 26 general purpose registers, extendible to 54
- 32-bit auxiliary register space for single-cycle, unarbitrated data storage and retrieval
ARC FPX Floating Point ExtensionsView more information on ARC FPX DSP Extensions- 16- and 32-bit MUL and MAC instructions
- Parallel execution of MUL, MAC and other ALU operations
- Saturating arithmetic instructions
- Zero overhead loop support
ARC XY Advanced DSP Subsystem- Full DSP performance using configurable banks of XY memory
- Eliminate DSP and logic blocks
- Consolidate development environment
- Includes ARC DSPlib with extensions such as: Dual FFT, Viterbi, CRC, 24x24MAC
View more information on the ARC XY Subsystem
Host Interface/Debug Features
- Software and hardware breakpoints with cascadable triggers
- JTAG interface to host tools
- Debug host can access all registers and CPU memory
- Supported by leading debuggers including Green Hills Software and MetaWare®
- SmaRT real-time trace facility
System Interface- Configurable port complies with industry standard AMBA/AHB or BVCI
- Slave interfaces exposed for loading optional instruction and data CCMsRight-hand sidebar
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