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Extendibility

Extendibility is the freedom for designers to add extensions of their own design to the ARC processor core. ARC offers flexibility to extend the core's instruction set, register set, auxiliary registers, and condition code logic, to create a processor highly tuned for the specific application. By accelerating inner loop or repetitive software in hardware via custom extensions, the designer can get more work done per instruction to allow performance unattainable by fixed architecture cores. Alternatively, the designer may elect to get the same amount of work done, but greatly reduce the clock frequency to conserve power. Performance increases or frequency reduction of up to 100 times are possible with intelligent use of the extendibility of the ARC cores.

Extensions are created directly in SystemC or Verilog using the Extension Wizard within the ARChitect Processor Configurator. No detailed knowledge of the ARC pipeline is needed to create these instructions. The designer simply chooses the type of extension, codes the functionality, and the Wizard will create a library directly usable by the ARChitect tool.

Example Extensions

Compound Instructions:

Compound instructions are created by collapsing sequences into a single instruction. A simple example is a Field Extract FEX command. Using typical RISC instructions, the compiler must AND the data with a field mask, then SHIFT the result to the lowest bits in the resulting word. A custom instruction can be created to do both the AND and SHIFT in a single instruction. This will cut execution time and code space in half compared to separate instructions.

SIMD Instructions:

Single Instruction Multiple Data (SIMD) custom instructions allow parallel execution of instructions. Typical RISC processors must execute an instruction sequence multiple times in series to process a set of data. With ARC's extendibility, instructions can be created that will operate on multiple operands of 16 or 8 bits in parallel packed into a 32-bit word. In addition, by creating multiple extension registers, instructions can be made 64 bits, 128 bits or even wider to include many operands for the parallel operation.

Integrated Coprocessor Instructions:

Coprocessors of any size and any pipeline length can be tightly coupled to the ARC processor through registers mapped into auxiliary register space, or through control data passed to the coprocessor as operand data. The return data can be routed to extension core registers to allow the ARC processor to continue executing instructions in parallel with the coprocessor. Scoreboarding of the return registers ensures all race hazards are avoided in hardware.

Wide Application Specific Instructions:

Combinations of the above instruction types and application specific interfaces are only limited by the user's creativity to provide unique differentiation for their products.

Here are two examples:

• Instructions receive data directly into extension core registers, 512 bytes at a time, and are fed into wide ALUs to provide full packet checking and classification in a single cycle without paying LD instruction penalties.
• Data pumped directly into ARC XY memory over direct memory interface ports, and perform Quad/Add/Compare/Select functions for Turbo Decode applications.

The architectural choices are left wide open to the user.