Products & Solutions
Configurability
To be successful in today’s system-on-chip (SoC) marketplace, designers must deliver silicon that is differentiated from the competition, consumes as little power as possible and has low production cost. Increasingly, SoC designers are turning to ARC International’s patented configurable processors and subsystems – and away from “fixed architecture alternatives” – to meet these challenges and create products that offer a strategic competitive advantage.
With ARC’s revolutionary configuration tool, the ARChitect™ Processor Configurator, SoC designers can easily create in a minutes a processor or subsystem from a standard menu of options. Cache size and features, interrupts, extension instructions, DSP features, timers, and many other features can be specified. And, designers can add features they need and to remove features they do not need for their application. Performance, size and power tradeoffs can be quickly made to define an optimum solution for any application. The result will invariably be a smaller die area, lower power and a lower production cost than is possible with a fixed architecture core.
Configurability Example: ARC™ 625D Core
Processor:
- Register file type and size
- Number of interrupts and pins
- Reset state
- Endianness
Cache:
- Cache type: Instruction and/or Data
- Size: 2k -32k Bytes
- Ways: 1 - 4
- Line Length: 16 - 128 bytes
Closely Coupled Memory:
- Instruction RAM: 1k - 512k bytes
- Data RAM: 2k - 32k bytes
Instructions:
- NORM - find the first "0" in a 32 bit word
- SWAP - switch locations of the top and bottom 16 bit fields
- MULT32 - fast 32 x 32 bit multiplier
DSP Functions:
- 24x24 MAC
- Dual 16x16 MAC
- 32x16 MAC
- Extended Arithmetic Package
- Dual Viterbi Butterfly
- CRC Acceleration
- Audio Acceleration Package
- XY Memory 1-2 Banks, 1k - 32k bytes, single or dual ported
Peripherals:
Bus Components:
Debug:
- JTAG interface
- Actionpoints
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